EEPROMs (acronym for Electrically Erasable Programmable Read Only Memories) or EAROMs (acronym for Electrically Alterable ROM=electrically alterable read only memo-ries), so-called flash memories, are known in a variety of embodiment variants from the prior art. EEPROM/flash memories are generally divided into rows and columns, each crossover point of columns and rows constituting a memory cell.
The respective columns of an EEPROM/flash memory are referred to as bit lines. These bit lines are terminated by a so-called sense amplifier. Said sense amplifier serves for evaluating the content of a respec-tively selected memory cell.
By way of example, a so-called 1 kbit memory comprises a total of 1024 individual EEPROM/EAROM memory cells with 32 rows and 32 columns or bit lines. Each bit line is assigned a sense amplifier, so that the 1 kbit memory has a total of 32 sense amplifiers. Each bit line in the memory array thus comprises, in accordance with the number of rows, 32 individual EEPROM/EAROM memory cells which are connected in parallel and with which a single sense amplifier is in each case connected in series.
In addition to the actual memory, which is usually formed by a memory transistor, each EEPROM/EAROM memory cell comprises a selection device, preferably a high-voltage switching transistor, by means of which the EEPROM/EAROM memory cell can be selected. In addition to the function of activating the read-out path, the selection device, in particular the high-voltage switching transistor, serves as a high-voltage protection device for the sense amplifier during erasure.
A sense amplifier comprises a comparison device, which compares the current intensity of a current flowing via the selected EEPROM/EAROM memory cell with that of a reference current and outputs a logic “0” or “1”, on the basis of the result of the comparison (the current intensity via the selected EEPROM/EAROM memory cell is greater or less than the reference current intensity).
There is often additionally present in each bit line a circuit device, which is usually formed as a so-called cascode transistor, which is provided for preventing “floating” of the bit line, that is to say for setting a defined potential on the bit line even when the bit line is not selected, and furthermore for increasing the read-out speed of the sense amplifier.
The read-out process is explained below with reference to FIG. 4 of the drawing.
FIG. 4 shows a sense amplifier 2 connected to a bit line 1 with a single memory cell S.
In accordance with the explanations above, the memory cell S comprises a memory transistor M1 with a floating gate (not illustrated here) and a high-voltage switching transistor M2 (in each case n-channel MOSFETs of the enhancement-mode type, MOSFET=acronym for Metal Oxide Semiconductor Field Effect Transistor), the drain-source channels D1, S1, D2, S2 of which are connected in series, the drain D1 of the memory transistor M1 being connected to the drain D2 of the high-voltage switching transistor M2.
In accordance with the explanations above, the sense amplifier 2 comprises a cascode transistor M3 (n-channel MOSFET of the enhancement-mode type), a current comparator 22 and two current mirrors 12 and 14.
Each current mirror 12, 14 is formed, in a manner that is customary per se, with the aid of two transistors M4, M5 (p-channel MOSFETs of the enhancement-mode type) and M6, M7 (n-channel MOSFETs of the enhancement-mode type), respectively, whose gates G4, G5 and G6, G7, respectively, are connected to one another and in the case of whose respective input-side transistor M4, M6 the gate G4, G6 is connected to the drain D4, D6.
The current comparator 22 is essentially formed by the two output-side transistors M5, M7 of the abovementioned current mirrors 12, 14, the drain D5 of the output-side transistor M5 of the current mirror 12 being connected to the drain D7 of the output-side transistor M7 of the current mirror 14.
The individual circuit blocks mentioned above are connected up to one another as follows:
The source S2 of the high-voltage switching transistor M2 of the memory cell S is connected to the source S3 of the cascode transistor M3. The drain D3 of the cascode transistor M3 is connected to the drain D4 of the input-side transistor M4 of the first current mirror 12. The substrate terminals B1, B2, B3, B6, B7 of all the NMOS transistors M1, M2, M3, M6, M7 each having a drain, source, gate and substrate terminal D1, D2, D3, D6, D7, S1, S2, S3, S6, S7, G1, G2, G3, G6, G7, B1, B2, B3, B6, B7 are in each case connected to a reference potential 18. The substrate terminals B4, B5 of the PMOS transistors M4, M5 each having a drain, source, gate and substrate terminal D4, D5, S4, S5, G4, G5, B4, B5 are at operating voltage UB.
The source S1 of the memory transistor M1 of the memory cell S and also the source terminals S6, S7 of the two transistors M6, M7 of the second current mirror 14 are at the reference potential 18. The two source terminals S4, S5 of the transistors M4, M5 of the first current mirror 12 are at the operating voltage UB provided by an operating voltage source 16. The operating voltage UB is generally approximately 5 V. A cascode voltage Ucascode, 21 provided by a cascode voltage source 21 is present at the gate G3 of the cascode transistor M3. The cascode voltage Ucascode,21 is dependent on the state of the memory cells. It is typically approximately 1.9 V in the control state. A fixedly predetermined drive voltage having a magnitude of typically Uref=1.25V (e.g. bandgap voltage) which is provided by a voltage source 19 is present at the gate G1 of the memory transistor M1. Interposed between the reference potential 18 and the source S2 of the high-voltage switching transistor M2 is a current sink 34 with a current I2, which holds the cascode transistor M3 at the operating point, which is intended to prevent “floating” of the bit line.
The read-out of the memory cell S, and in particular of the content of the memory transistor M1, is effected in accordance with the description below:
The memory cell S is selected as a result of the gate G2 of the high-voltage switching transistor M2 being driven with a selection voltage Usel provided by a selection voltage source 20. The high-voltage switching transistor M2 is in the on state. As a result, a read current Iread driven by the operating voltage UB flows through the read-out path 5 formed by the drain-source paths D4, S4, D3, S3, D2, S2, D1, S1 of the transistors M4, M3, M2, M1. The read current intensity Iread is determined by the threshold voltage Uth,M1 of the memory transistor M1, which was set by preceding erasure (normally on state of the transistor M1 is necessary for current flow). A reference current Iref provided by a reference current source 7 simultaneously flows in the opposite direction.
The read current Iread predetermined by the memory transistor M1 and the reference current Iref flowing in the opposite direction are mirrored (mirror direction 17) with the aid of the first current mirror 12 into the comparator current path 23 formed by the source-drain path S5, D5 of the output-side mirror transistor M5 of the first current mirror 12 and the source-drain path S7, D7 of the output-side mirror transistor M7 of the second current mirror 14 and are ready there as mirrored differential current (Iread−Iref)g. At the same time, the reference current Iref provided by the reference current source 7 is mirrored (mirror direction 15) with the aid of the second current mirror 14 into the comparator current path 23 formed by the source-drain path S5, D5 of the output-side mirror transistor M5 of the first current mirror 12 and the source-drain path S7, D7 of the output-side mirror transistor M7 of the second current mirror 14 and is ready there as mirrored reference current Iref,g.
If Iread=0, it follows that (Iread−Iref)g=Iref,g<0. In this case, the output voltage Uout=0 is present at the drain D5 of the output-side mirror transistor M5 of the first current mirror 12 and the sense amplifier 2 outputs a logic “0”. If Iread>Iref, it follows that (Iread−Iref)g=Iref,g>0. In this case, the operating voltage UB is dropped across the mirror transistor M7 and the comparator output Aout is at operating or supply voltage Uout=UB and the sense amplifier 2 outputs a logic “1”.
A reference circuit arrangement 3* for generating the reference current Iref that is usually used according to the prior art is illustrated in FIG. 5.
The reference circuit arrangement 3* for generating the reference current Iref essentially comprises a simulation of the read-out path 5 of the circuit arrangement according to FIG. 4 that is formed by the drain-source paths D4, S4, D3, S3, D2, S2, D1, S1 of the transistors M4, M3, M2, M1.
In concrete terms, the reference circuit arrangement 3* according to the prior art comprises a reference memory transistor M1,ref and a reference high-voltage switching transistor M2,ref, which together form a reference memory cell Sref, a reference cascode transistor M3,ref and a current mirror 10 corresponding to the type described above with two p-channel MOS field effect transistors M4,ref, M5,ref of the enhancement-mode type.
The gates G4,ref and G5,ref of the two field effect transistors M4,ref, M5,ref of the current mirror 10 are connected to one another. The gate G4,ref of the input-side transistor M4,ref is connected to the drain D4,ref thereof.
The source S2,ref of the reference high-voltage switching transistor M2,ref of the reference memory cell Sref is connected to the source S3,ref of the reference cascode transistor M3,ref. The drain D3,ref of the reference cascode transistor M3,ref is connected to the drain D4,ref of the input-side transistor M4,ref of the current mirror 10. The substrate terminals B1,ref, B2,ref, B3,ref of all the NMOS transistors M1,ref, M2,ref, M3,ref each having a drain, source, gate and substrate terminal D1,ref . . . D3,ref, S1,ref . . . S3,ref, G1,ref . . . G3,ref, B1,ref . . . B3,ref are connected to the reference potential 18. The substrate terminals B4,ref, B5,ref of all the PMOS transistors each having a drain, source, gate and substrate terminal D4,ref, D5,ref, S4,ref, S5,ref, G4,ref, G5,ref B4,ref, B5,ref are connected to the operating voltage potential UB,ref.
The source S1,ref of the reference memory transistor M1,ref of the reference memory cell Sref is at the reference potential 18. The two source terminals S4,ref, S5,ref of the transistors M4,ref, M5,ref of the reference current mirror 10, in the same way as the gate G2,ref of the reference high-voltage switching transistor M2,ref, are at an operating voltage UB,ref provided by a reference operating voltage source 11, said operating voltage being identical to that from the operating voltage source UB of the sense amplifier 2. The operating voltage UB=UB,ref is generally approximately 5 V. A cascode voltage Ucascode,9 provided by a reference cascode voltage source 9 is present at the gate G3,ref of the reference cascode transistor M3. Said cascode voltage Ucascode,9 is typically Ucascode,9=1.9 V in the control state, as above. A fixedly predetermined reference drive voltage Uref provided by a voltage source 8 can be applied to the gate G1,ref of the reference memory transistor M1,ref, said reference drive voltage being chosen to be identical to the drive voltage Uref in the circuit arrangement 2 according to FIG. 4.
The reference current Iref is generated by a current Iref,0 flowing via the reference memory transistor M1,ref on account of the voltage drop across the read-out path simulation 5ref formed by the source-drain paths S1,ref, D1,ref, S2,ref, D2,ref, S3,ref, D3,ref, S4,ref, D4,ref of the reference transistors M1,ref, M2,ref, M3,ref, M4,ref. Said current Iref,0 is mirrored (mirror direction 13) with the aid of the reference current mirror 10 from the input-side transistor M4,ref to the output-side mirror transistor M5,ref. The current flowing through the mirror transistor M5,ref forms the reference current Iref, which can be tapped off at the drain D5,ref of the mirror transistor M5,ref. This terminal representing the actual reference current source is identified by the reference symbol 7 in FIG. 5.
In order to set the reference current Iref to a desired value, the so-called target current intensity Itarget, the reference memory transistor M1,ref is brought to the normally on state by erasure.
The threshold voltage Uth,M1,ref of the reference memory transistor M1,ref, which can be altered by means of the erasure, is responsible for the current-carrying capacity of the reference EEPROM/EAROM cell:                erasure with a high erase voltage means a strongly negative threshold voltage Uth,M1,ref. The channel of the reference memory transistor M1,ref is strongly normally on.        erasure with a low erase voltage means a weakly negative threshold voltage Uth,M1,ref. The channel of the reference memory transistor M1,ref is weakly normally on.        
This influence of the erase voltage on the current-carrying capacity of the reference memory cell Sref or the reference memory cells (typically a total of eight reference memory cells of the type illustrated in FIG. 5 are used for generating the reference current for the entire memory, said reference memory cells being connected in parallel) is utilized in the customary principle of reference current generation. In this case, the reference memory cell(s), which are generally all situated on the same semiconductor chip, is/are trimmed to the target current Itarget during testing by the cycle erasure—current measurement, said target current being fed into the sense amplifier 2 as reference current Iref.
The erasure of the reference memory cell(s) Sref is effected by the gate G1,ref of the reference memory transistor M1,ref being put at reference potential 18 and the source S1,ref of the reference memory transistor M1,ref momentarily having a high voltage of the erase voltage, applied to it. Said voltage is generally approximately 20 V.
For the subsequent current measurement, a defined reference voltage Uref (e.g. the bandgap voltage of approximately 1.25 eV) is applied to the gate G1,ref of the EEPROM cell M1,ref (illustrated in FIG. 5).
If the desired target current intensity Itarget is not reached after the first cycle, that is to say if the measured current intensity Imeas is less than the target current intensity Itarget, erasure is effected once again, but this time with a high erase voltage. The consequence of this is that the magnitude of the threshold voltage Uth,M1,ref decreases and the cell current Iref,0 rises. This adjustment may last for a few cycles until the target current Itarget is reached. The reference cell Sref then remains untouched over the lifetime.
Although the method described above and also the circuit arrangement illustrated in FIG. 5 have basically proved to be worthwhile, various weak points still exist.
In particular, the reference current is a current trimmed to an absolute value and is therefore greatly dependent on the state of the reference cells. As a result of the complicated current adjustment during testing, the process dependence, that is to say the variation of the component properties on account of certain production tolerances, can be eliminated for the most part.
During the lifetime of the EEPROM, the so-called “floating gate” of the memory transistor loses charge, which leads to a threshold voltage increase and thus to a lower current-carrying capacity of the memory cell.
This process is known as “data retention”. In order to be able to maintain the required read-out speed over the lifetime of the EEPROM, it is necessary to allow for a certain bias in the dimensioning of the threshold voltage. This has the effect that the overall current consumption rises. This results from the relationship whereby the magnitude of the threshold voltage during erasure is proportional to the read-out current and thus proportional to the read-out time.
Moreover, temperature changes and operating voltage fluctuations cause in some instances considerable fluctuations of the reference current.
In order to set the reference current correctly despite all the influences, complicated technological examinations are necessary over the “operating window” of the EEPROM cells.